ATLAS-TRT Front-End Electronics
ASDBLR cards
PostScript Files
o Overview
o Tension-plate
v Stamp-card
vASDBLR card
vPS plots
oOlder versions
oProduction versions
oIGES files
oGerber Files
oMGC Design
oDTMROC card
oASTRAL card
o Roof Board
o Chip Development
o Prototype boards
o Software
o Glossary and Index
o Links
l1.eps Layer1 (top-side) layout.
l1bond.eps Layer1 (top-side) layout with bond-diagram included.
l1comp.eps Layer1 (top-side) component placement.
l1place.eps Layer1 (top-side) component placement including traces.
l1meas.eps Layer1 (top-side) dimensions and measurements.
l1signal.eps Layer1 (top-side) connector assignment.
l2.eps Layer2 (1st inner-layer) layout.
l3.eps Layer3 (2nd inner-layer) layout. Ground-plane, negative plot.
l4.eps Layer4 (3rd inner-layer) layout. Combined ground and power-plane, negative plot
l5.eps Layer5 (4th inner-layer) layout.
l6.eps Layer6 (bottom) layout.
l6bond.eps Layer6 (bottom) layout with bond-diagram included.
l6meas.eps Layer6 (bottom) dimensions.
l6comp.eps Layer6 (bottom) component placement.
l6place.eps Layer6 (bottom) component placement with traces.
physical.eps Side and top-views of asdblr-card. Same as above but BW. Schematic drawing. A3-size Schematic drawing. A4-size View over pads, top-side. View over pads, bottom-side. View of bare ASDBLR-chip, padnumbers according to View of ASDBLR-chip connections in PLCC64-package
©1998 Particle Physics Department, Lund University
Comments to: Lund Electronics group,