ATLAS-TRT Front-End Electronics
Production ASDBLR cards
PostScript Files
o Overview
o Tension-plate
v Stamp-card
vASDBLR card
vPS plots
oOlder versions
oProduction versions
oIGES files
oGerber Files
oMGC Design
oDTMROC card
oASTRAL card
o Roof Board
o Chip Development
o Prototype boards
o Software
o Glossary and Index
o Links
ASDBLR-daughterboard v 2.1 is in the tender-process and production will start Aug 10th.
Expected delivery end of september. Layer1 (top-side) layout. Layer1 (top-side) layout with bond-diagram included. Layer1 (top-side) component placement including traces. Layer1 (top) solder-mask. Layer2 (1st inner-layer) layout. Layer3 (2nd inner-layer) layout. Ground-plane, negative plot. Layer4 (3rd inner-layer) layout. Combined ground and power-plane, negative plot Layer4 (3rd inner-layer) layout. Signal-traces in ground-plane
  Note!  5 ASDBLR-daughterboards will be manufactured with some extra traces in the power-plane (layer 4) which will serve as test-signal injecting capacitors for the input-pins.
These 5 boards will be evaluated for increased noise and/or crosstalk. Layer5 (4th inner-layer) layout. Layer6 (bottom) layout. Layer6 (bottom) layout with bond-diagram included. Layer6 (bottom) solder-mask. Layer6 (bottom) component placement with traces.
©1998 Particle Physics Department, Lund University
Comments to: Lund Electronics group,