ATLAS-TRT Front-End Electronics
ASDBLR cards
PostScript Files, Old
o Overview
o Tension-plate
v Stamp-card
vASDBLR card
vPS plots
vOlder versions
oProduction versions
oIGES files
oGerber Files
oMGC Design
oDTMROC card
oASTRAL card
o Roof Board
o Chip Development
o Prototype boards
o Software
o Glossary and Index
o Links
design 960813: db_desc.txt A more detailedfile-description of the 960813-files
  l1.eps Layer1 (top-side) layout.
  l1b.eps Layer1 (top-side) layout including bonding.
  l2.eps Layer2 (1st inner-layer) layout.
  l3.eps Layer3 (2nd inner-layer) layout. Ground-plane, negative plot.
  l4.eps Layer4 (3rd inner-layer) layout. Combined ground and power-plane, negative plot
  l5.eps Layer5 (4th inner-layer) layout.
  l6.eps Layer6 (bottom) layout.
  l6b.eps Layer6 (bottom) layout with bond-diagram included.
  db_all.eps All layers at the same time (!).
  db_bond.eps Bonding layers.
  schematic.eps Schematic drawing.
  db_cross.txt ASCII cross-section
design 960925: db_desc.txt A more detailed file-description of the 960925-files
  db_bond1.eps Layer1 (top-side) bonding.
  db_bond2.eps Layer6 (bottom-side) bonding.
  db_l1.eps Layer1 (top-side) layout.
  db_l1b.eps Layer1 (top-side) layout including bonding.
  db_l1place.eps Layer1 (top-side) layout, bonding and placement.
  db_l2.eps Layer2 (first inner-layer) layout.
  db_l3.eps Layer3 (second inner-layer) layout, ground plane.
  db_l4.eps Layer4 (third inner-layer) layout, split power-plane.
  db_l5.eps Layer5 (fourth inner-layer) layout.
  db_l6.eps Layer6 (bottom-side) layout.
  db_l6b.eps Layer6 (bottom-side) layout including bonding.
  db_l6place.eps Layer6 (bottom-side) layout, bonding and placement.
  db_sch.eps Schematic drawing.
Version 2.0: Pad diagram of ASDBLR chip. Package bonding diagram of ASDBLR chip.
  channel_mapping.eps Channel mapping of inputs.
  l1bond.eps Bonding, top layer.
  l1comp.eps Component placement, top layer.
  l1place.eps Component placement + traces, top layer.
  l1signal.eps Signal placement on top connector.
  l1meas.eps Measurements, top layer.
  l1.eps Artwork, Layer 1.
  l2.eps Artwork, Layer 2.
  l3.eps Artwork, Layer 3.
  l4.eps Artwork, Layer 4.
  l5.eps Artwork, Layer 5.
  l6.eps Artwork, Layer 6.
  l6bond.eps Bonding, bottom layer.
  l6comp.eps Component placement, bottom layer.
  l6place.eps Component placement + traces, bottom layer.
  l6meas.eps Measurements, bottom layer.
  physical.eps Board overview, side and top views. Same in B&W. Schematic plot, size A4 (210x297mm). Schematic plot, size A3 (420x297mm). Gasselect pads, top layer. Gasselect pads, bottom layer.
©1999 Particle Physics Department, Lund University
Comments to: Lund Electronics group,