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DTMROC Integrated Circuit

This subsection describes the functionality and gives the performances of the current version of the DTMROC. It has been decided recently that the production version of the DTMROC will have two significant changes as compared to the present version:

 1. It will act as a transient digitiser on the low-level threshold signal with a 3 ns binning (i.e. the value of the signal is stored every 3 ns);

 2. The TTC information will be transmitted using the protocol defined for the SCT in order to minimise the number of cables and to have as uniform a system as possible.

Neither of these changes will significantly affect this chip as the heart of the transient digitiser electronics is the same as the one used for the drift-time measurement (even simpler as it elimi- nates one encoding stage). The main difference will be the size of the level-1 pipeline and the number of storage positions which have to be foreseen in the output derandomiser in order to remain within the 1% dead-time limit.

Principle

The DTMROC consists of two parts:
  • One part derived from the RD6 readout chip. This part measures the drift time and delays it in a pipeline.
  • One part derived from the Transition Radiation Detector Support (TRDS) chip produced by Rutherford Appleton Laboratory, which supports the ASDBLR.

    The task of the first, here called the time measurement and readout part, is to receive the ternary encoded information from the ASDBLR, recover the high and low threshold signals, and measure the timing of the low threshold signal at the rate of the beam crossing (40.08 MHz).

    The status of the low and high threshold discriminator outputs, together with the drift time measurement and a bit indicating the occurrence of a rising edge on the low threshold signal, are stored and delayed in a memory for the level-1 trigger latency of 128 beam crossings. Conceptually one may think of this delay as a pipeline. Data corresponding to a given bunch crossing flow through the pipeline and reach the end in phase with the level-1 trigger decision (L1A) which also corresponds to this bunch crossing. If there is a trigger Accept, three subsequent timeslices corresponding to the event that caused the trigger are stored in a derandomiser (i.e. fifo) for read out. If there is no valid trigger, the timeslice at the end of the pipeline is discarded.
    A new trigger may arrive while the outputs are busy sending data to the read-out driver (ROD). In this case the timeslices belonging to the later trigger should be stored in the derandomiser for later readout. The DTMROC is able to store a number of pending events in this manner.
    The second part of the DTMROC, here called support part, deals with communication with the rest of the system, supplies reference currents for the ASDBLR, test pulses, etc.
    More extensive documentation of the DTMROC can be found in [12-81].

    Time measurement and readout circuitry

    The time measurement and readout circuitry itself consists of a number of subparts: digital time measurement (DTM), latch, pipeline memory, derandomiser, and drivers and receivers which are described in the following sub-headings.

    DTM

    The drift time measurement circuit is made up of a delay-locked-loop (DLL) and a Gray encoder as shown in Figure 1.

    Figure 1 schematics of delay-locked loop (DLL).

    The BX clock is delayed exactly 1 clock cycle in a chain of delay elements. By storing the state of the nodes between the delay elements when the input signal occurs, one obtains a measurement of the arrival time with a binning of 1/8 of the cycle time, e.g. 25ns/8 = 3.15ns. To control the total delay both the direct and the delayed BX clock signal are fed to an edge-sensitive phase detector. The phase detector compares the direct fed BX clock with the delayed BX clock and outputs a signal proportional to the phase difference. This signal controls the delay chain so that the total delay is exactly 1 clock cycle. Finally a gray encoder encodes the state of the 8 nodes to a 3 digit value which is fed to the latch.

    Latch

    The latch’s inputs are connected to the low and high threshold signals and to the 3 bits coming from the DTM. When the low threshold signal is high, the latch latches the inputs. The outputs of the latch are fed into the input of the pipeline memory.

    Pipeline memory

    The pipeline is made of 2 memory banks which are alternately used to make sure that read and write cycles can occur at the same time.

    Drivers and receivers

    To be able to operate the circuit without injecting noise into the very sensitive preamplifier situated a few mm away, low-level differential drivers and receivers are utilised. There are two kinds of receivers- a ternary current receiver and a differential voltage receiver. The ternary receiver is used to receive the output from the ASDBLR to the DTMROC, which is communicated with ternary (tri-level) encoded differential current signals. The differential voltage receiver receives all other signals, such as the Clock and L1A and is sensitive to voltage swings between 50mV and 400mV. It is compatible with applicable parts of the low-voltage differential signal (LVDS) standard.
    The driver is a differential voltage driver with swing adjustable between 50mV and 400mV. The swing is controlled by a bias current set by an external resistor and, when properly adjusted, compatible with LVDS.

    Support Circuitry

    The support circuitry handles all communication with the back-end system, via the so called Parameter Control Interface. This part controls different circuits in the chip, namely reference currents to set the ASDBLR thresholds, the two testpulse circuits, a testpattern insertion into the pipeline and some other adjustable parameters.

    Reference currents for threshold adjustment

    To be able to adjust finely the performance of the detector there are 4 8-bit DACs on the chip that define reference currents for the low and high thresholds on the two ASDBLRs connected to each DTMROC.

    Testpulse circuitry

    There are two independent testpulse circuits on the chip, each connected to odd and even chan- nels on the ASDBLRs via small capacitors. There are separate magnitude settings and enables for each circuit, but the trigger signal is common for both of them.

    Testpattern insertion

    To be able to adjust the timing between an individual DTMROC and the ROD there is the possibility to inject a special testpattern, 101010101010..., which upon reception in the ROD can be used to adjust the timing of the ROD receiver. This testpattern is inserted into the beginning of the pipeline and a subsequent trigger is needed to read it out. The testpattern is also very useful from a testing point of view since a large part of the silicon area must be working in order to get the correct output. Thus a second testpattern is implemented which simply is the reverse of the first i.e. 01010101010101... The testpattern selection and enabling is selectable via the Parameter and Control Interface.

    Other controllable features

    The present version is intermediate and all specifications are not yet determined. Therefore some extra functionality needs to be controllable in this version, such as serial readout speed. The speed can be either 20, 40 or 80 MHz.

    Timing and trigger handling

    The current version of the timing, trigger and parameter control electronics is described here. It will be updated to the final ATLAS Inner Detector protocol for the next version of the circuit.

    LHC clock

    The BX clock is received by the differential voltage receiver and distributed around the chip with a regular clock tree. There is no provision for fine delay adjustment of the clock as it is done in the off-detector electronics and there is one BX feed for a small detector area (1 feed per barrel module, and 1 feed every 1/32 nd of each end-cap wheel).

    L1A and test pulse

    The L1A trigger and testpulse trigger signals are received with the differential voltage receiver and fed directly to the appropriate circuitry on chip.

    Parameters control

    All signals to/from the parameter control are standard CMOS/TTL but at a much slower clock frequency (1 MHz). They are intended to be used sparsely during data acquisition. In the production version of the chip, these signals will also be low-level differential.

    Resets

    There are two resets on the chip, one general and one for the DTM part only (to recover from a lock failure of the DLL). The general reset is asynchronous; the DTM reset is synchronous with respect to the BX clock.

    Readout

    The data are serially readout via a twisted pair cable to the ROD. The read-out is self-triggered, i.e. when a trigger is received the readout starts as soon as possible, with a minimum of 1 BX clock cycle between subsequent readouts.

    Derandomiser depth

    The depth of the derandomiser is determined by the rate of the trigger, the speed of the serial readout link and the acceptable dead-time and event losses. The goal is to have a dead-time of less than 1% when the trigger rate is 75 kHz. Given these conditions, the correct length of the derandomiser can be calculated as the answer of a queuing theory problem. The results are shown in Table 1. As can be seen, a derandomiser depth of 7 events at 40 MHz serial readout speed is required. The drivers themselves can communicate at 80 MHz, but it has not yet been demonstrated that the whole system works at 80 Mhz. Therefore 40 MHz has been chosen as a conservative solution.

    Depth Loss (%) at 20MHz Loss (%) at 40MHz Loss (%) at 80MHz
    3 38.1 9.5 1.26
    4 36.4 5.2 0.25
    5 35.8 3.0 0.05
    6 35.6 1.8 0.01
    7 35.5 1.0 0.00
    8 35.5 0.6 0.00

    Table 1

    Performance

    Recent measurements show that the present version of the DTMROC performs correctly. The measurements were done with a custom built tester, where each input to the DTMROC is fed with a 250ps resolution signal. Five channels on two different chips were tested with a total number of about 1250000 events. Each channel was scanned starting before BX 0, stepping the input-pulse 250 ps every event until the input-pulse was outside timeslice 2. The results of the measurements are shown in Figure 2. As one can see the DTM follows the delay as expected, with a bin mean value of 3.13 ns and a sigma of 0.55 ns.

    Figure 2 DTMROC TDR measurement.

    Design validation and test procedures for the next version of the DTMROC

    The validation of the circuit will be carried out at several levels of hierarchy. First a high-level description in VHDL 1 (digital parts) and HDL-A 2 (analogue parts) will be produced and the chip will be simulated to verify the functional performance. When all system aspects are properly verified, the translation into more and more detailed description of the different blocks will take place, with appropriate reviews between each step, until finally masks for the production are created. There are two kinds of tests foreseen to be made on the chip, one extensive test to be made on a small number of engineering samples to verify that the design is correct and another test, much simpler and faster, to verify that every chip is free of manufacture related errors. The test vectors are derived from a behavioural VHDL-model of the chip.


    Text and pictures extracted from Atlas Inner Detector, Technical design Report



    Documentation of the DTMROC

    Specification for DTMROC chip, previous version, manufactured in AMS 1.0 micron process.
    The current version can be found at Geneva University.

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    ©1997 Particle Physics Department, Lund University
    Comments to: Lund Electronics group, bjorn@quark.lu.se