ATLAS-TRT Front-End Electronics
DTMROC cards
PostScript Files
o Overview
o Tension-plate
v Stamp-card
oASDBLR card
vDTMROC card
vPS plots
oProduction version
oIGES files
oGerber Files
oMGC Design
oASTRAL card
o Roof Board
o Chip Development
o Prototype boards
o Software
o Glossary and Index
o Links
l1.eps Layer1 (top-side) layout.
l1bond.eps Layer1 (top-side) layout with bond-diagram included.
l1comp.eps Layer1 (top-side) component placement.
l1meas.eps Layer1 (top-side) dimensions and measurements.
l1signal.eps Layer1 (top-side) connector assignment.
solder1.eps Layer1 (top-side) solder mask.
l2.eps Layer2 (1st inner-layer) layout.
l3.eps Layer3 (2nd inner-layer) layout. Ground-plane, positive plot.
l4.eps Layer4 (bottom) layout.
l4conn.eps Layer4 (bottom) connector placement.
l4signal.eps Layer4 (bottom) connector assignment.
physical.eps Side and top-views of dtmroc-card. Same as above but BW. Schematic drawing. A3-size
©1997 Particle Physics Department, Lund University
Comments to: Lund Electronics group,