ATLAS-TRT Front-End Electronics
DTMROC cards
PostScript Files
o Overview
o Tension-plate
v Stamp-card
oASDBLR card
vDTMROC card
vPS plots
vProduction version
oIGES files
oGerber Files
oMGC Design
oPictures
oASTRAL card
o Roof Board
o Chip Development
o Prototype boards
o Software
o Glossary and Index
 
 
o Links
l1.ps Layer1 (top-side) layout.
place1.ps Layer1 (top-side) component placement.
l1bond.ps Layer1 (top-side) layout with bond-diagram included.
solder1.ps Layer1 (top-side) solder mask.
l2.ps Layer2 (1st inner-layer) layout.
l3.ps Layer3 (2nd inner-layer) layout. Ground-plane, negative plot.
l4.ps Layer4 (bottom) layout.
solder4.ps Layer4 (bottom) layout. Soldemask
place4.ps Layer4 (bottom) layout. Component placement
ATLAS
©1997 Particle Physics Department, Lund University
Comments to: Lund Electronics group, bjorn@quark.lu.se