ATLAS-TRT Front-End Electronics
DTMROC cards
PostScript Files
o Overview
o Tension-plate
v Stamp-card
oASDBLR card
vDTMROC card
vPS plots
vProduction version
oIGES files
oGerber Files
oMGC Design
oASTRAL card
o Roof Board
o Chip Development
o Prototype boards
o Software
o Glossary and Index
o Links Layer1 (top-side) layout. Layer1 (top-side) component placement. Layer1 (top-side) layout with bond-diagram included. Layer1 (top-side) solder mask. Layer2 (1st inner-layer) layout. Layer3 (2nd inner-layer) layout. Ground-plane, negative plot. Layer4 (bottom) layout. Layer4 (bottom) layout. Soldemask Layer4 (bottom) layout. Component placement
©1997 Particle Physics Department, Lund University
Comments to: Lund Electronics group,