ATLAS Front-End Electronics
DTMROC tester
o Overview
o Tension-plate
o Stamp-card
o Roof Board
o Chip Development
v Prototype boards
oCooling prototype
vDTMROC tester
oversion 0
oversion 1
vversion 2
vPS plots
oGerber Files
oMGC Design
oversion 3
oHP82000 boards
oMiscellaneous test-boards
o Software
o Glossary and Index
o Links
Description Root schematic sheet Schematic sheet over bus-interface.
Designed to interface with our home-developed LUCIUS processor board (using a 68HC11). clock generating circuit Signal delay for test-inputs The delay-element to the former schematic LED interface for optical readout OBSOLETE Memory configuration Power supply Printer interface Root schematic sheet Root schematic sheet Data shaper DTMROC (ZIF) chip socket and connections Programming chain First layer of PCB-layout Second layer of PCB-layout, power-plane Third layer of PCB-layout Fourth layer of PCB-layout Fifth layer of PCB-layout, power-plane Sixth layer of PCB-layout Silk-screen, component side Silk-screen, solder side
©1997 Particle Physics Department, Lund University
Comments to: Lund Electronics group,