# Settings common to all ALTROs in all FECs # FORMAT # All values are decimail! Might change for some settings #Zero suppression threshold and offset #ZSTHR.OFFSET Offset to be added to the signal #ZSTHR.ZS_THR Zero suppression threshold #Second baseline correction threshold #BCTHR.THR_LO Lower threshold of the acc. window #BCTHR.THR_HI Upper threshold of the acc. window #Trigger configuration #TRCFG.ACQ_START Number of cycles to wait before start #TRCFG.ACQ_SHIFT shift the start of aquisition depending on ALTRO # 0 = no shift # else # chip 0 1 2 3 4 5 6 7 # shift 0 1 2 3 0 1 2 3 i.e. each side of the card # #TRCFG.ACQ_END Cycles to sample #Data path configuration #DPCFG.ZS_CFG bits 0-1:glitch filter # bits 2-4:presamples # bits 5-6:postsamples # bit 7:enable zero suppression #DPCFG.BC2_CFG bits 0-1:presamples excluded from 2nd baseline # bits 2-5:postsamples excluded from 2nd baseline # bit 6: enable second baseline #DPCFG.BC1_CFG bits 0-3:first baseline mode # when bit is set. ADC value is inverted #BFNPT.PWSV <0,1> when set, power save #BFNPT.FLT_EN <0,1> enable digital filter #BFNPT.NBUF <0,1> 0: 4 buffers, 1: 8 buffers #BFNPT.PTRG <0-15> Pretrigger samples # ZSTHR.OFFSET 0 #ZSTHR.ZS_THR 8 #ZSTHR.ZS_THR 10 #2009.02.28 ZSTHR.ZS_THR 3 #BCTHR.THR_LO 3 #BCTHR.THR_HI 2 BCTHR.THR_LO 0 BCTHR.THR_HI 0 TRCFG.ACQ_START 0 TRCFG.ACQ_SHIFT 0 TRCFG.ACQ_END 300 #TRCFG.ACQ_END 1000 #TRCFG.ACQ_END 108 # DPCFG bits 0-1: glitch, 2-4:postsamples, 5-6:presamples, 7: zerosup # 202 = 0xCA 2 2 2 1 # zero suppression on #DPCFG.ZS_CFG 202 #DPCFG.ZS_CFG 201 #DPCFG.BC2_CFG 0 #DPCFG.BC1_CFG 0 # din - fpd do not use lookup table #DPCFG.FBCM 0 #-> f(din) - fpd = use lookup table subtract fixed pedestal DPCFG.FBCM 8 # f(din-vpd) - fpd = use lookup table subtract self pedestal #DPCFG.FBCM 9 # f(t) - fpd = read pedestal memory as data #DPCFG.FBCM 10 DPCFG.POLARITY 0 DPCFG.SBPRE 0 DPCFG.SBPOST 0 DPCFG.SBENB 0 DPCFG.GLITCH 2 # PRESAMLPES 0-3, POSTSAMPLES 0-7 #DPCFG.ZSPRE 2 #2008.02.28 #DPCFG.ZSPOST 2 #2008.02.28 DPCFG.ZSPRE 3 DPCFG.ZSPOST 7 # zero skip enable bit DPCFG.ZSENB 1 BFNPT.PWSV 0 BFNPT.FLT_EN 0 BFNPT.NBUF 0 #BFNPT.PTRG 7 BFNPT.PTRG 0