We have run with three different settings of the reference voltages.
This was done to move the pedestals slightly within the ADC range
to see how channels with wide pedestal behave as a function of ADC value.

refnom: refn=250mV, cm=750 mV, refp=1250mV
(DAC settings 125,375,625).
pedestals:
ch-all-chip10061-ped-preamp0gain0shaper0decay0.5-refnom.pdf
time sweep channel 6 which is OK:
ch6-10061-1-34168.pdf
time sweep channel 8 with wide pedestal:
ch8-10061-1-34169.pdf


ref25 : refn=200mV, cm=700 mV, refp=1200mV
(DAC settings 100,350,600).
pedestals:
ch-all-chip10061-ped-preamp0gain0shaper0decay0.5-ref25.pdf


ref25up : refn=300mV, cm=800mV, refp=1300mV
(DAC settings 150,400,650).
pedestals:
ch-all-chip10061-ped-preamp0gain0shaper0decay0.5-ref25up.pdf
time sweep channel 14 with wide pedestal: ch14-10061-1-34208-ref25up.pdf

Pedestals/rms for the diffent reference voltages:

   refnom     	  ref25   	      ref25up
0  880.6/0.69 	  881.4/0.66	      879.6/0.63
1  853.5/2.14	  844.3/3.36	      857.9/0.35  848=11 0101 0000	      
2  850.3/0.69	  847.3/0.76	      851.9/1.46	      
3  867.7/4.36	  858.1/4.09	      870.0/0.04  864=11 0110 0000
4  853.8/0.76	  847.6/0.63	      860.1/0.47
5  857.0/1.41	  851.8/0.54	      861.9/1.03
6  853.4/0.62	  851.9/1.74	      856.0/0.65
7  871.5/0.56	  870.8/0.43	      872.0/0.56
8  876.3/5.22	  881.1/0.83	      869.7/0.65  880=11 0111 0000
9  864.6/0.55	  860.5/1.03	      866.8/0.46 
10 867.6/0.61	  867.5/1.13	      866.7/0.47
11 882.3/0.49	  886.2/0.56	      879.4/0.79
12 862.0/0.46	  860.0/0.81	      863.6/0.70
13 854.2/1.76	  852.7/2.48	      854.2/1.39
14 876.7/0.78	  878.5/0.78	      871.4/3.98 ?
15 863.5/0.50	  861.7/0.56	      864.6/0.48

There is a small change in the mean of the pedestals for those channels
that are always good. Different channels have large rms for the
diffent settings of refvoltages, these channels do then have larger
differences in the mean of the pedestal.

In the rightmost column have I tried to assoiciate changes of bits 0-3 from 0000
for channels with wide pedestals.
Not found any obvious such result for channel 14.

In the plot for chip 63 channel, first batch as tested both on CERN testboard
and protomcm:
http://www.hep.lu.se/eudet/pictures/protomcm/tests-20170915/plots-20180319.pdf
See plot 4: time sweep pulser+gain3+preampmode ch9
For some ADC values at regular intervals are "spikes".

On the 2chipcard was the chip numbers mounted:
19 and 32. 32 was removed (I think) . Batch is  FR 19 18 (i.e. second batch).
See picture: 12727-00eb1.jpg.

Plots for chip 19:
http://www.hep.lu.se/eudet/pictures/protomcm/chip19/plots-20180626.pdf

plots for chip32:
http://www.hep.lu.se/eudet/pictures/protomcm/chip32/plots-20180703.pdf