# # Command file to initialize the SRU after power up. # # SRU.ID 0 SRU id (must be 1 at the moment) # # REGISTER 1 = set, 0 = unset SRU.DTCCLKEN.DTC0 1 DTC clock_en bit0 SRU.DTCCLKEN.DTC1 1 DTC clock_en bit1 SRU.DTCCLKEN.DTC2 1 DTC clock_en bit2 SRU.DTCCLKEN.DTC3 0 DTC clock_en bit3 SRU.DTCCLKEN.DTC4 0 DTC clock_en bit4 SRU.DTCCLKEN.DTC5 0 DTC clock_en bit5 SRU.DTCCLKEN.DTC6 0 DTC clock_en bit6 SRU.DTCCLKEN.DTC7 0 DTC clock_en bit7 SRU.DTCCLKEN.DTC8 0 DTC clock_en bit8 SRU.DTCCLKEN.DTC9 0 DTC clock_en bit9 SRU.DTCCLKEN.DTC10 0 DTC clock_en bit10 SRU.DTCCLKEN.DTC11 0 DTC clock_en bit11 SRU.DTCCLKEN.DTC12 0 DTC clock_en bit12 SRU.DTCCLKEN.DTC13 0 DTC clock_en bit13 SRU.DTCCLKEN.DTC14 0 DTC clock_en bit14 SRU.DTCCLKEN.DTC15 0 DTC clock_en bit15 SRU.DTCCLKEN.DTC16 0 DTC clock_en bit16 SRU.DTCCLKEN.DTC17 0 DTC clock_en bit17 SRU.DTCCLKEN.DTC18 0 DTC clock_en bit18 SRU.DTCCLKEN.DTC19 0 DTC clock_en bit19 SRU.DTCCLKEN.DTC20 0 DTC clock_en bit20 SRU.DTCCLKEN.DTC21 0 DTC clock_en bit21 SRU.DTCCLKEN.DTC22 0 DTC clock_en bit22 SRU.DTCCLKEN.DTC23 0 DTC clock_en bit23 SRU.DTCCLKEN.DTC24 0 DTC clock_en bit24 SRU.DTCCLKEN.DTC25 0 DTC clock_en bit25 SRU.DTCCLKEN.DTC26 0 DTC clock_en bit26 SRU.DTCCLKEN.DTC27 0 DTC clock_en bit27 SRU.DTCCLKEN.DTC28 0 DTC clock_en bit28 SRU.DTCCLKEN.DTC29 0 DTC clock_en bit29 SRU.DTCCLKEN.DTC30 0 DTC clock_en bit30 SRU.DTCCLKEN.DTC31 0 DTC clock_en bit31 SRU.DTCCLKEN.DTC32 0 DTC clock_en bit32 SRU.DTCCLKEN.DTC33 0 DTC clock_en bit33 SRU.DTCCLKEN.DTC34 0 DTC clock_en bit34 SRU.DTCCLKEN.DTC35 0 DTC clock_en bit35 SRU.DTCCLKEN.DTC36 0 DTC clock_en bit36 SRU.DTCCLKEN.DTC37 0 DTC clock_en bit37 SRU.DTCCLKEN.DTC38 0 DTC clock_en bit38 SRU.DTCCLKEN.DTC39 0 DTC clock_en bit39 # Write the register SRU.WR.DTCCLKEN1 # DTCCLKEN1 0-19 SRU.WR.DTCCLKEN2 # DTCCLKEN2 20-39 # Send a word align command. #SRU.WR.WALIGN # # # REGISTER 1 = set, 0 = unset SRU.RDOMASK.DTC0 1 DTC mask bit0 SRU.RDOMASK.DTC1 1 DTC mask bit1 SRU.RDOMASK.DTC2 1 DTC mask bit2 SRU.RDOMASK.DTC3 1 DTC mask bit3 SRU.RDOMASK.DTC4 1 DTC mask bit4 SRU.RDOMASK.DTC5 1 DTC mask bit5 SRU.RDOMASK.DTC6 1 DTC mask bit6 SRU.RDOMASK.DTC7 1 DTC mask bit7 SRU.RDOMASK.DTC8 1 DTC mask bit8 SRU.RDOMASK.DTC9 1 DTC mask bit9 SRU.RDOMASK.DTC10 1 DTC mask bit10 SRU.RDOMASK.DTC11 1 DTC mask bit11 SRU.RDOMASK.DTC12 1 DTC mask bit12 SRU.RDOMASK.DTC13 1 DTC mask bit13 SRU.RDOMASK.DTC14 1 DTC mask bit14 SRU.RDOMASK.DTC15 1 DTC mask bit15 SRU.RDOMASK.DTC16 1 DTC mask bit16 SRU.RDOMASK.DTC17 1 DTC mask bit17 SRU.RDOMASK.DTC18 1 DTC mask bit18 SRU.RDOMASK.DTC19 1 DTC mask bit19 SRU.RDOMASK.DTC20 1 DTC mask bit20 SRU.RDOMASK.DTC21 1 DTC mask bit21 SRU.RDOMASK.DTC22 1 DTC mask bit22 SRU.RDOMASK.DTC23 1 DTC mask bit23 SRU.RDOMASK.DTC24 1 DTC mask bit24 SRU.RDOMASK.DTC25 1 DTC mask bit25 SRU.RDOMASK.DTC26 1 DTC mask bit26 SRU.RDOMASK.DTC27 1 DTC mask bit27 SRU.RDOMASK.DTC28 1 DTC mask bit28 SRU.RDOMASK.DTC29 1 DTC mask bit29 SRU.RDOMASK.DTC30 1 DTC mask bit30 SRU.RDOMASK.DTC31 1 DTC mask bit31 SRU.RDOMASK.DTC32 1 DTC mask bit32 SRU.RDOMASK.DTC33 1 DTC mask bit33 SRU.RDOMASK.DTC34 1 DTC mask bit34 SRU.RDOMASK.DTC35 1 DTC mask bit35 SRU.RDOMASK.DTC36 1 DTC mask bit36 SRU.RDOMASK.DTC37 1 DTC mask bit37 SRU.RDOMASK.DTC38 1 DTC mask bit38 SRU.RDOMASK.DTC39 1 DTC mask bit39 # Write to the register SRU.WR.DTCRDOMASK1 # DTCMASK 0-19 SRU.WR.DTCRDOMASK2 # DTCMASK 20-39 # SRU Config register settings #SRU.SRUCFG.CLKSRCSEL 0 # Use the TLU clk SRU.SRUCFG.CLKSRCSEL 1 # Use the brd clk SRU.SRUCFG.RDOCMDOPT 0 # 0 for now. May need to change later #SRU.SRUCFG.TRIGMODE 1 # Hardware trigger SRU.SRUCFG.TRIGMODE 0 # Software trigger. Will use a packet to trigger the SRU, while debugging. SRU.SRUCFG.EVENT_ACK_EN 1 # Enable the event acknowledge mechanism (acknowledge with writes to register 46) SRU.SRUCFG.SPILLEN 1 # Enable Spill control SRU.SRUCFG.EVENTNUMBERSEL 0 # 0 - internal event counter, 1 - TLU event counter #SRU.SRUCFG.EVENTNUMBERSEL 1 # 0 - internal event counter, 1 - TLU event counter SRU.SRUCFG.PARREQ 0 # Something related to TTC triggering. Keep it 0 for now. SRU.SRUCFG.CDHVER 0 # Something related to TTC triggering. Keep it 0 for now. # Write to the register SRU.WR.SRUREGCFG # Write to SRU register # Configure the trigger timing windows. SRU.TRIGL1TW.LOW 120 # Taken from the simulation SRU.TRIGL1TW.HIGH 5000 # Taken from the simulation #SRU.TRIGL1TW.HIGH 7000 # Taken from the simulation SRU.TRIGL2TW.LOW 200 # Taken from the simulation SRU.TRIGL2TW.HIGH 8000 # Taken from the simulation SRU.WR.TRIGL1TW # Write to SRU register SRU.WR.TRIGL2TW # Write to SRU register # Test trigger congiguration, since we are using software triggering. SRU.TESTTRIGCFG0.L0LATENCY 200 #Taken from simulations SRU.TESTTRIGCFG0.L1LATENCY 4500 #Taken from simulations #SRU.TESTTRIGCFG0.L1LATENCY 4000 #Taken from simulations #SRU.TESTTRIGCFG0.L1LATENCY 9000 #Taken from simulations SRU.WR.TESTTRIGCFG0 # Write to SRU register SRU.TESTTRIGCFG1.L2LATENCY 4550 #Jonas: reduced this because the trigger unit doesn't see the UDP transaction otherwise #SRU.TESTTRIGCFG1.L2LATENCY 4600 #Jonas: reduced this because the trigger unit doesn't see the UDP transaction otherwise #SRU.TESTTRIGCFG1.L2LATENCY 9050 #Jonas: reduced this because the trigger unit doesn't see the UDP transaction otherwise #SRU.TESTTRIGCFG1.L2LATENCY 6000 #Taken from simulation SRU.TESTTRIGCFG1.TRIGSEQSET 13 #4'b1101, L1, no second L1, L2, CHRDO #SRU.TESTTRIGCFG1.TRIGSEQSET 5 #4'b0101, L1, no second L1, L2, no CHRDO # In actuality, the TRIGSEQSET bits mean: # bit0: Send Saltro sample trigger immediately (L0) # bit1: Send Saltro sample trigger after L0 Latency (Don't activate bit 0 and 1 simultaneously) # bit2: Send capture trigger to Saltro after L1 Latency # bit3: Generate L2accept trigger (which we don't use) after L2 Latency # With SRUCFG.RDOCMDOPT = 0, the readout command is sent to the MCM immediately after the capture trigger. # = 1, it is sent immediately after the L2Accept trigger SRU.WR.TESTTRIGCFG1 # Write to SRU register #SRU.PTRIGCFG.PERIOD 20000 SRU.PTRIGCFG.PERIOD 200 SRU.PTRIGCFG.PTRIGEN 0 SRU.WR.PTRIGCFG # Write to SRU register # Test pulse congiguration. SRU.TESTPULSECFG.START 40 #Taken from simulations SRU.TESTPULSECFG.WIDTH 40 #Taken from simulations SRU.TESTPULSECFG.EN 1 #Taken from simulations SRU.WR.TESTPULSECFG # Write to SRU register # Set the READOUT IP SRU.READOUTIP.IP1 192‬ # SRU.READOUTIP.IP2 168 #‬ SRU.READOUTIP.IP3 4 # SRU.READOUTIP.IP4 11 # SRU.WR.READOUTIP 1 # # Read the registers again to confirm they were changed. # REGISTER 1 - Read the register, 0 - Ignore the line. SRU.RD.DTCCLKEN1 1 DTCCLKEN 0-19 SRU.RD.DTCCLKEN2 1 DTCCLKEN 20-39 # REGISTER SRU.RD.DTCRDOMASK1 1 DTCMASK 0-19 SRU.RD.DTCRDOMASK2 1 DTCMASK 20-39 # REGISTER SRU.RD.SRUREGCFG 1 SRU.RD.TRIGL1TW 1 SRU.RD.TRIGL2TW 1 SRU.RD.TESTTRIGCFG0 1 SRU.RD.TESTTRIGCFG1 1 SRU.RD.PTRIGCFG 1 #Just read the serial number. SRU.RD.SN 1 SRU.RD.READOUTIP 1 SRU.RD.TESTPULSECFG 1 #Do synkscan (channel bit from bit 24, mode bit 16, value bits 0-15) SRU.PSSCAN.CHANNEL 0 SRU.PSSCAN.MODE 0 SRU.PSSCAN.VALUE 141 #SRU.PSSCAN.MODE 1 #SRU.PSSCAN.VALUE 10 SRU.WR.PSSCAN # Write to SRU register # Send a word align command. SRU.WR.WALIGN #