Timing measurements
===================

1
=
Blue: dtc_trig_p
Green: dtc_clk_p
Measured on the connector on the signal from SRU

5 ns per divsion:
20190221_113130r.jpg

2 ns per division:
20190221_113237r.jpg

The clock and trigger/line are not shifted.

2
=
In the code mcmtop.v I assigned:
assign adcclk_out[2] = dtc_clk;
assign adcclk_out[3] = dtc_trig;
assign adcclk_out[4] = rdoclk;
assign adcclk_out[5] = trig_test;

Blue: dtc_trig
Green: adcclk_out[4] i.e. rdoclk
20190221_113826r.jpg

3
=
Blue: adcclk_out[3] .i.e. dtc_trig
Green: rodclk[1]
20190221_114323r.jpg

There is a slight shift between rodclk[1] and adcclk_out[4].
adcclk and rdoclk are on different banks.

4
=
Blue: adcclk_out[3] .i.e. dtc_trig
Green:  adcclk_out[2] = dtc_clk;
20190221_130503r.jpg

5
=
I have also tried in dtc_rx.v:
assign trig_test=clkin;
endmodule

to get it out on adcclk_out[5] as assigned above,
but I do not get any clock on it, but it sometimes gives a level of 800 ns.

6
=
So I am not sure where things are sampled, I assumed one should sample in
the middle of the trigger/control "pulse" to be safe.

7
=
I do not know enough about verilog programming, to be sure I assign correctly.