#ChipScope Core Inserter Project File Version 3.0
#Fri Apr 08 15:07:48 CEST 2022
Project.device.designInputFile=/home/ise/Projekt/EUDET/SRU/merged/SaltroUdp/sru/sru_top_cs.ngc
Project.device.designOutputFile=/home/ise/Projekt/EUDET/SRU/merged/SaltroUdp/sru/sru_top_cs.ngc
Project.device.deviceFamily=17
Project.device.enableRPMs=true
Project.device.outputDirectory=/home/ise/Projekt/EUDET/SRU/merged/SaltroUdp/sru/_ngo
Project.device.useSRL16=true
Project.filter.dimension=19
Project.filter<0>=spill*
Project.filter<10>=Fast|
Project.filter<11>=Fast
Project.filter<12>=spill
Project.filter<13>=spill?edge
Project.filter<14>=edge
Project.filter<15>=EDGE
Project.filter<16>=dge
Project.filter<17>=*edge
Project.filter<18>=*edge*
Project.filter<1>=u_sru_cmd_par/spill*
Project.filter<2>=
Project.filter<3>=u_sru_cmd_par/Fast*
Project.filter<4>=u_sru_cmd_par/*Cmd*
Project.filter<5>=u_sru_cmd_par/*Cmd
Project.filter<6>=u_sru_cmd_par/*edge
Project.filter<7>=u_sru_cmd_par/*
Project.filter<8>=u_sru_cmd_par
Project.filter<9>=Fast*
Project.icon.boundaryScanChain=1
Project.icon.enableExtTriggerIn=false
Project.icon.enableExtTriggerOut=false
Project.icon.triggerInPinName=
Project.icon.triggerOutPinName=
Project.unit.dimension=3
Project.unit<0>.clockChannel=u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx bitclk
Project.unit<0>.clockEdge=Rising
Project.unit<0>.dataChannel<0>=spill_IBUF
Project.unit<0>.dataChannel<10>=u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx FastCmd
Project.unit<0>.dataChannel<11>=u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx FastCmd_buffer
Project.unit<0>.dataChannel<12>=u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx FastCmd_ack
Project.unit<0>.dataChannel<13>=spill_sync_dd
Project.unit<0>.dataChannel<14>=u_sru_cmd_par/spill_d
Project.unit<0>.dataChannel<15>=u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx u_dtc_dout_ser pdata_reg<5>
Project.unit<0>.dataChannel<16>=u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx u_dtc_dout_ser pdata_reg<4>
Project.unit<0>.dataChannel<17>=u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx u_dtc_dout_ser pdata_reg<3>
Project.unit<0>.dataChannel<18>=u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx u_dtc_dout_ser pdata_reg<2>
Project.unit<0>.dataChannel<19>=u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx u_dtc_dout_ser pdata_reg<1>
Project.unit<0>.dataChannel<1>=spill_sync_d
Project.unit<0>.dataChannel<20>=u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx u_dtc_dout_ser pdata_reg<0>
Project.unit<0>.dataChannel<21>=u_sru_40dtc_top/u_dtc_chrdo_fsm rdocmd
Project.unit<0>.dataChannel<22>=u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx rdocmd_buffer
Project.unit<0>.dataChannel<23>=u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx rdocmd_ack
Project.unit<0>.dataChannel<24>=u_sru_cmd_par/srucfg<0>
Project.unit<0>.dataChannel<25>=u_sru_cmd_par/srucfg<3>
Project.unit<0>.dataChannel<26>=u_sru_cmd_par/srucfg<4>
Project.unit<0>.dataChannel<27>=u_sru_cmd_par/srucfg<5>
Project.unit<0>.dataChannel<28>=u_sru_cmd_par/srucfg<8>
Project.unit<0>.dataChannel<29>=u_sru_cmd_par/srucfg<9>
Project.unit<0>.dataChannel<2>=u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx FastCmdCode<7>
Project.unit<0>.dataChannel<30>=u_sru_cmd_par/FastCmd_i
Project.unit<0>.dataChannel<31>=u_sru_cmd_par/FastCmd_reg<15>
Project.unit<0>.dataChannel<3>=u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx FastCmdCode<6>
Project.unit<0>.dataChannel<4>=u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx FastCmdCode<5>
Project.unit<0>.dataChannel<5>=u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx FastCmdCode<4>
Project.unit<0>.dataChannel<6>=u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx FastCmdCode<3>
Project.unit<0>.dataChannel<7>=u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx FastCmdCode<2>
Project.unit<0>.dataChannel<8>=u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx FastCmdCode<1>
Project.unit<0>.dataChannel<9>=u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_tx FastCmdCode<0>
Project.unit<0>.dataDepth=4096
Project.unit<0>.dataEqualsTrigger=false
Project.unit<0>.dataPortWidth=32
Project.unit<0>.enableGaps=false
Project.unit<0>.enableStorageQualification=false
Project.unit<0>.enableTimestamps=false
Project.unit<0>.timestampDepth=0
Project.unit<0>.timestampWidth=0
Project.unit<0>.triggerChannel<0><0>=spill_sync_d
Project.unit<0>.triggerConditionCountWidth=0
Project.unit<0>.triggerMatchCount<0>=1
Project.unit<0>.triggerMatchCountWidth<0><0>=0
Project.unit<0>.triggerMatchType<0><0>=1
Project.unit<0>.triggerPortCount=1
Project.unit<0>.triggerPortIsData<0>=true
Project.unit<0>.triggerPortWidth<0>=1
Project.unit<0>.triggerSequencerLevels=16
Project.unit<0>.triggerSequencerType=0
Project.unit<0>.type=ilapro
Project.unit<1>.clockChannel=u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder bitclkdiv
Project.unit<1>.clockEdge=Rising
Project.unit<1>.dataChannel<0>=u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder dtc_deser_dout<0>
Project.unit<1>.dataChannel<10>=u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder dtc_deser_dout<10>
Project.unit<1>.dataChannel<11>=u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder dtc_deser_dout<11>
Project.unit<1>.dataChannel<12>=u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder dtc_deser_dout<12>
Project.unit<1>.dataChannel<13>=u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder dtc_deser_dout<13>
Project.unit<1>.dataChannel<14>=u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder dtc_deser_dout<14>
Project.unit<1>.dataChannel<15>=u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder dtc_deser_dout<15>
Project.unit<1>.dataChannel<1>=u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder dtc_deser_dout<1>
Project.unit<1>.dataChannel<2>=u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder dtc_deser_dout<2>
Project.unit<1>.dataChannel<3>=u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder dtc_deser_dout<3>
Project.unit<1>.dataChannel<4>=u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder dtc_deser_dout<4>
Project.unit<1>.dataChannel<5>=u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder dtc_deser_dout<5>
Project.unit<1>.dataChannel<6>=u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder dtc_deser_dout<6>
Project.unit<1>.dataChannel<7>=u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder dtc_deser_dout<7>
Project.unit<1>.dataChannel<8>=u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder dtc_deser_dout<8>
Project.unit<1>.dataChannel<9>=u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder dtc_deser_dout<9>
Project.unit<1>.dataDepth=4096
Project.unit<1>.dataEqualsTrigger=true
Project.unit<1>.dataPortWidth=16
Project.unit<1>.enableGaps=false
Project.unit<1>.enableStorageQualification=false
Project.unit<1>.enableTimestamps=false
Project.unit<1>.timestampDepth=0
Project.unit<1>.timestampWidth=0
Project.unit<1>.triggerChannel<0><0>=u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder dtc_deser_dout<0>
Project.unit<1>.triggerChannel<0><10>=u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder dtc_deser_dout<10>
Project.unit<1>.triggerChannel<0><11>=u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder dtc_deser_dout<11>
Project.unit<1>.triggerChannel<0><12>=u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder dtc_deser_dout<12>
Project.unit<1>.triggerChannel<0><13>=u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder dtc_deser_dout<13>
Project.unit<1>.triggerChannel<0><14>=u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder dtc_deser_dout<14>
Project.unit<1>.triggerChannel<0><15>=u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder dtc_deser_dout<15>
Project.unit<1>.triggerChannel<0><1>=u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder dtc_deser_dout<1>
Project.unit<1>.triggerChannel<0><2>=u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder dtc_deser_dout<2>
Project.unit<1>.triggerChannel<0><3>=u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder dtc_deser_dout<3>
Project.unit<1>.triggerChannel<0><4>=u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder dtc_deser_dout<4>
Project.unit<1>.triggerChannel<0><5>=u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder dtc_deser_dout<5>
Project.unit<1>.triggerChannel<0><6>=u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder dtc_deser_dout<6>
Project.unit<1>.triggerChannel<0><7>=u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder dtc_deser_dout<7>
Project.unit<1>.triggerChannel<0><8>=u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder dtc_deser_dout<8>
Project.unit<1>.triggerChannel<0><9>=u_sru_40dtc_top/dtc_partition[0].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_decoder dtc_deser_dout<9>
Project.unit<1>.triggerConditionCountWidth=0
Project.unit<1>.triggerMatchCount<0>=1
Project.unit<1>.triggerMatchCountWidth<0><0>=0
Project.unit<1>.triggerMatchType<0><0>=0
Project.unit<1>.triggerPortCount=1
Project.unit<1>.triggerPortIsData<0>=true
Project.unit<1>.triggerPortWidth<0>=16
Project.unit<1>.triggerSequencerLevels=16
Project.unit<1>.triggerSequencerType=0
Project.unit<1>.type=ilapro
Project.unit<2>.clockChannel=u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser bitclkdiv
Project.unit<2>.clockEdge=Rising
Project.unit<2>.dataChannel<0>=u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser dtc_deser_dout<0>
Project.unit<2>.dataChannel<10>=u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser dtc_deser_dout<10>
Project.unit<2>.dataChannel<11>=u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser dtc_deser_dout<11>
Project.unit<2>.dataChannel<12>=u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser dtc_deser_dout<12>
Project.unit<2>.dataChannel<13>=u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser dtc_deser_dout<13>
Project.unit<2>.dataChannel<14>=u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser dtc_deser_dout<14>
Project.unit<2>.dataChannel<15>=u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser dtc_deser_dout<15>
Project.unit<2>.dataChannel<1>=u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser dtc_deser_dout<1>
Project.unit<2>.dataChannel<2>=u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser dtc_deser_dout<2>
Project.unit<2>.dataChannel<3>=u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser dtc_deser_dout<3>
Project.unit<2>.dataChannel<4>=u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser dtc_deser_dout<4>
Project.unit<2>.dataChannel<5>=u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser dtc_deser_dout<5>
Project.unit<2>.dataChannel<6>=u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser dtc_deser_dout<6>
Project.unit<2>.dataChannel<7>=u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser dtc_deser_dout<7>
Project.unit<2>.dataChannel<8>=u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser dtc_deser_dout<8>
Project.unit<2>.dataChannel<9>=u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser dtc_deser_dout<9>
Project.unit<2>.dataDepth=4096
Project.unit<2>.dataEqualsTrigger=true
Project.unit<2>.dataPortWidth=16
Project.unit<2>.enableGaps=false
Project.unit<2>.enableStorageQualification=false
Project.unit<2>.enableTimestamps=false
Project.unit<2>.timestampDepth=0
Project.unit<2>.timestampWidth=0
Project.unit<2>.triggerChannel<0><0>=u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser dtc_deser_dout<0>
Project.unit<2>.triggerChannel<0><10>=u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser dtc_deser_dout<10>
Project.unit<2>.triggerChannel<0><11>=u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser dtc_deser_dout<11>
Project.unit<2>.triggerChannel<0><12>=u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser dtc_deser_dout<12>
Project.unit<2>.triggerChannel<0><13>=u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser dtc_deser_dout<13>
Project.unit<2>.triggerChannel<0><14>=u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser dtc_deser_dout<14>
Project.unit<2>.triggerChannel<0><15>=u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser dtc_deser_dout<15>
Project.unit<2>.triggerChannel<0><1>=u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser dtc_deser_dout<1>
Project.unit<2>.triggerChannel<0><2>=u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser dtc_deser_dout<2>
Project.unit<2>.triggerChannel<0><3>=u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser dtc_deser_dout<3>
Project.unit<2>.triggerChannel<0><4>=u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser dtc_deser_dout<4>
Project.unit<2>.triggerChannel<0><5>=u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser dtc_deser_dout<5>
Project.unit<2>.triggerChannel<0><6>=u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser dtc_deser_dout<6>
Project.unit<2>.triggerChannel<0><7>=u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser dtc_deser_dout<7>
Project.unit<2>.triggerChannel<0><8>=u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser dtc_deser_dout<8>
Project.unit<2>.triggerChannel<0><9>=u_sru_40dtc_top/dtc_partition[1].u_dtc_master_top/u_dtc_master_rx/u_dtc_rx_deser dtc_deser_dout<9>
Project.unit<2>.triggerConditionCountWidth=0
Project.unit<2>.triggerMatchCount<0>=1
Project.unit<2>.triggerMatchCountWidth<0><0>=0
Project.unit<2>.triggerMatchType<0><0>=0
Project.unit<2>.triggerPortCount=1
Project.unit<2>.triggerPortIsData<0>=true
Project.unit<2>.triggerPortWidth<0>=16
Project.unit<2>.triggerSequencerLevels=16
Project.unit<2>.triggerSequencerType=0
Project.unit<2>.type=ilapro