INFO:sim:172 - Generating IP...
Applying current project options...
Finished applying current project options.
WARNING:sim - A core named 'brdclk_pll' already exists in the project. Output
   products for this core may be overwritten.
Resolving generics for 'brdclk_pll'...
WARNING:sim - A core named 'brdclk_pll' already exists in the project. Output
   products for this core may be overwritten.
Applying external generics to 'brdclk_pll'...
Delivering associated files for 'brdclk_pll'...
WARNING:sim - Component clk_wiz_v3_6 does not have a valid model name for
   Verilog synthesis
Delivering EJava files for 'brdclk_pll'...
Delivered 3 files into directory
/home/ise/Projekt/EUDET/SRU/merged/SaltroUdp/sru/ipcore_dir/tmp/_cg/brdclk_pll
Delivered 1 file into directory
/home/ise/Projekt/EUDET/SRU/merged/SaltroUdp/sru/ipcore_dir/tmp/_cg/brdclk_pll
Generating ASY schematic symbol...
Loading device for application Rf_Device from file '6vlx130t.nph' in environment
/opt/Xilinx/14.7/ISE_DS/ISE/.
INFO:sim:949 - Finished generation of ASY schematic symbol.
Generating SYM schematic symbol for 'brdclk_pll'...
Generating ISE project...
XCO file found: brdclk_pll.xco
XMDF file found: brdclk_pll_xmdf.tcl
Adding
/home/ise/Projekt/EUDET/SRU/merged/SaltroUdp/sru/ipcore_dir/tmp/_cg/brdclk_pll.a
sy -view all -origin_type imported
Adding
/home/ise/Projekt/EUDET/SRU/merged/SaltroUdp/sru/ipcore_dir/tmp/_cg/brdclk_pll.u
cf -view all -origin_type created
Adding
/home/ise/Projekt/EUDET/SRU/merged/SaltroUdp/sru/ipcore_dir/tmp/_cg/brdclk_pll.v
-view all -origin_type created
INFO:HDLCompiler:1845 - Analyzing Verilog file
   "/home/ise/Projekt/EUDET/SRU/merged/SaltroUdp/sru/ipcore_dir/tmp/_cg/brdclk_p
   ll.v" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
Adding
/home/ise/Projekt/EUDET/SRU/merged/SaltroUdp/sru/ipcore_dir/tmp/_cg/brdclk_pll.v
eo -view all -origin_type imported
INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off.
   Please set the new top explicitly by running the "project set top" command.
   To re-calculate the new top automatically, set the "Auto Implementation Top"
   property to true.
Top level has been set to "/brdclk_pll"
Generating README file...
Generating FLIST file...
INFO:sim:948 - Finished FLIST file generation.
Launching README viewer...
Moving files to output directory...
Finished moving files to output directory
Wrote CGP file for project 'brdclk_pll'.