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#
# Xilinx Core Generator version 14.7
# Date: Tue Mar 21 21:46:29 2017
#
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#
#  This file contains the customisation parameters for a
#  Xilinx CORE Generator IP GUI. It is strongly recommended
#  that you do not manually alter this file as it may cause
#  unexpected and unsupported behavior.
#
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#
#  Generated from component: xilinx.com:ip:mig:3.92
#
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#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc6vlx130t
SET devicefamily = virtex6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = ff1156
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -1
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT MIG_Virtex-6_and_Spartan-6 family Xilinx,_Inc. 3.92
# END Select
# BEGIN Parameters
CSET component_name=dram_controller
CSET xml_input_file=./dram_controller/user_design/mig.prj
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2013-10-13T18:46:09Z
# END Extra information
GENERATE
# CRC: 4b32a143