<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">

  <header>
    <!-- ISE source project file created by Project Navigator.             -->
    <!--                                                                   -->
    <!-- This file contains project source information including a list of -->
    <!-- project source files, project and process properties.  This file, -->
    <!-- along with the project source files, is sufficient to open and    -->
    <!-- implement in ISE Project Navigator.                               -->
    <!--                                                                   -->
    <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
  </header>

  <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>

  <files>
    <file xil_pn:name="dram_controller/user_design/rtl/axi/axi_ctrl_addr_decode.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="1"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="1"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="1"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/axi/axi_ctrl_read.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="2"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="2"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="2"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/axi/axi_ctrl_reg.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="3"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="3"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="3"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/axi/axi_ctrl_reg_bank.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/axi/axi_ctrl_top.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="5"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="5"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="5"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/axi/axi_ctrl_write.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="6"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="6"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="6"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/axi/axi_mc.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="7"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="7"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="7"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/axi/axi_mc_ar_channel.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="8"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="8"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="8"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/axi/axi_mc_aw_channel.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="9"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="9"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="9"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/axi/axi_mc_b_channel.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="10"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="10"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="10"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/axi/axi_mc_cmd_arbiter.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="11"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="11"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="11"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/axi/axi_mc_cmd_fsm.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="12"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="12"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="12"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/axi/axi_mc_cmd_translator.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="13"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="13"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="13"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/axi/axi_mc_incr_cmd.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="14"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="14"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="14"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/axi/axi_mc_r_channel.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="15"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="15"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="15"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/axi/axi_mc_simple_fifo.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="16"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="16"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="16"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/axi/axi_mc_w_channel.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="17"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="17"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="17"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/axi/axi_mc_wr_cmd_fsm.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="18"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="18"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="18"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/axi/axi_mc_wrap_cmd.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="19"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="19"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="19"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/axi/ddr_a_upsizer.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="20"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="20"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="20"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/axi/ddr_axi_register_slice.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="21"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="21"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="21"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/axi/ddr_axi_upsizer.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="22"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="22"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="22"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/axi/ddr_axic_register_slice.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="23"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="23"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="23"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/axi/ddr_carry_and.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="24"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="24"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="24"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/axi/ddr_carry_latch_and.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="25"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="25"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="25"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/axi/ddr_carry_latch_or.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="26"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="26"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="26"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/axi/ddr_carry_or.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="27"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="27"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="27"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/axi/ddr_command_fifo.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="28"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="28"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="28"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/axi/ddr_comparator.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="29"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="29"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="29"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="29"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/axi/ddr_comparator_sel.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="30"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="30"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="30"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="30"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/axi/ddr_comparator_sel_static.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="31"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="31"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="31"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="31"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/axi/ddr_r_upsizer.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="32"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="32"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="32"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="32"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="32"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/axi/ddr_w_upsizer.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="33"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="33"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="33"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="33"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/axi/fi_xor.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="34"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="34"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="34"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="34"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="34"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/controller/arb_mux.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="35"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="35"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="35"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="35"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="35"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/controller/arb_row_col.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="36"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="36"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="36"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="36"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="36"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/controller/arb_select.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="37"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="37"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="37"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="37"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="37"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/controller/bank_cntrl.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="38"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="38"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="38"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="38"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="38"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/controller/bank_common.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="39"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="39"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="39"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="39"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="39"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/controller/bank_compare.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="40"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="40"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="40"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="40"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="40"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/controller/bank_mach.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="41"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="41"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="41"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="41"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="41"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/controller/bank_queue.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="42"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="42"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="42"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="42"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="42"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/controller/bank_state.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="43"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="43"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="43"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="43"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="43"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/controller/col_mach.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="44"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="44"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="44"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="44"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="44"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/controller/mc.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="45"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="45"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="45"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="45"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="45"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/controller/rank_cntrl.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="46"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="46"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="46"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="46"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="46"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/controller/rank_common.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="47"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="47"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="47"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="47"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="47"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/controller/rank_mach.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="48"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="48"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="48"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="48"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="48"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/controller/round_robin_arb.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="49"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="49"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="49"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="49"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="49"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/ecc/ecc_buf.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="50"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="50"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="50"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="50"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="50"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/ecc/ecc_dec_fix.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="51"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="51"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="51"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="51"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="51"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/ecc/ecc_gen.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="52"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="52"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="52"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="52"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="52"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/ecc/ecc_merge_enc.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="53"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="53"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="53"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="53"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="53"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/ip_top/clk_ibuf.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="54"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="54"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="54"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="54"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="54"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/ip_top/ddr2_ddr3_chipscope.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="55"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="55"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="55"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="55"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="55"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/ip_top/dram_controller.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="56"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="56"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="56"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="56"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="56"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/ip_top/infrastructure.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="57"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="57"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="57"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="57"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="57"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/ip_top/iodelay_ctrl.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="58"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="58"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="58"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="58"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="58"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/ip_top/mem_intfc.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="59"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="59"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="59"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="59"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="59"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/ip_top/memc_ui_top.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="60"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="60"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="60"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="60"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="60"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/phy/circ_buffer.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="61"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="61"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="61"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="61"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="61"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/phy/phy_ck_iob.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="62"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="62"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="62"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="62"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="62"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/phy/phy_clock_io.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="63"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="63"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="63"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="63"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="63"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/phy/phy_control_io.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="64"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="64"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="64"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="64"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="64"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/phy/phy_data_io.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="65"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="65"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="65"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="65"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="65"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/phy/phy_dly_ctrl.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="66"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="66"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="66"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="66"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="66"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/phy/phy_dm_iob.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="67"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="67"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="67"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="67"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="67"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/phy/phy_dq_iob.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="68"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="68"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="68"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="68"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="68"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/phy/phy_dqs_iob.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="69"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="69"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="69"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="69"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="69"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/phy/phy_init.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="70"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="70"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="70"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="70"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="70"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/phy/phy_pd.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="71"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="71"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="71"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="71"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="71"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/phy/phy_pd_top.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="72"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="72"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="72"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="72"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="72"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/phy/phy_rdclk_gen.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="73"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="73"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="73"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="73"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="73"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/phy/phy_rdctrl_sync.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="74"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="74"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="74"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="74"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="74"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/phy/phy_rddata_sync.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="75"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="75"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="75"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="75"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="75"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/phy/phy_rdlvl.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="76"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="76"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="76"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="76"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="76"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/phy/phy_read.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="77"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="77"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="77"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="77"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="77"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/phy/phy_top.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="78"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="78"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="78"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="78"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="78"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/phy/phy_write.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="79"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="79"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="79"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="79"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="79"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/phy/phy_wrlvl.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="80"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="80"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="80"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="80"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="80"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/phy/rd_bitslip.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="81"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="81"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="81"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="81"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="81"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/ui/ui_cmd.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="82"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="82"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="82"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="82"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="82"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/ui/ui_rd_data.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="83"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="83"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="83"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="83"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="83"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/ui/ui_top.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="84"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="84"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="84"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="84"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="84"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/rtl/ui/ui_wr_data.v" xil_pn:type="FILE_VERILOG">
      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="85"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="85"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="85"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="85"/>
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="85"/>
    </file>
    <file xil_pn:name="dram_controller/user_design/par/dram_controller.ucf" xil_pn:type="FILE_UCF">
      <association xil_pn:name="Implementation" xil_pn:seqID="86"/>
    </file>
  </files>

  <properties>
    <property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
    <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Device" xil_pn:value="xc6vlx130t" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Device Family" xil_pn:value="Virtex6" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Implementation Top" xil_pn:value="Module|dram_controller" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Implementation Top File" xil_pn:value="dram_controller/user_design/rtl/ip_top/dram_controller.v" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/dram_controller" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Package" xil_pn:value="ff1156" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
    <property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
    <property xil_pn:name="Speed Grade" xil_pn:value="-1" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
    <!--                                                                                  -->
    <!-- The following properties are for internal use only. These should not be modified.-->
    <!--                                                                                  -->
    <property xil_pn:name="PROP_DesignName" xil_pn:value="dram_controller" xil_pn:valueState="non-default"/>
    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="virtex6" xil_pn:valueState="default"/>
    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2017-03-21T22:46:34" xil_pn:valueState="non-default"/>
    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="9C3F8ADC42C249C6AFEEEE8A964D0904" xil_pn:valueState="non-default"/>
    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
  </properties>

  <bindings>
    <binding xil_pn:location="/dram_controller" xil_pn:name="dram_controller/user_design/par/dram_controller.ucf"/>
  </bindings>

  <libraries/>

  <autoManagedFiles>
    <!-- The following files are identified by `include statements in verilog -->
    <!-- source files and are automatically managed by Project Navigator.     -->
    <!--                                                                      -->
    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
    <!-- project is analyzed based on files automatically identified as       -->
    <!-- include files.                                                       -->
  </autoManagedFiles>

</project>
