`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Module Name:    ResetEmu
// Designer: Jonas Nilsson
// Function: Provide a pulse with a duration of 2**23 clk cycles
//           Provide such an output pulse on power up
//////////////////////////////////////////////////////////////////////////////////
module ResetEmu
  (
	 input  clk,
	 input  pulse_in,
	 output pulse_out
   );

  reg     pulse_out_i = 1'b0;
  reg [23:0] cnt_i = 24'h0;

  assign pulse_out = pulse_out_i;

  parameter Idle_st     = 3'b001;
  parameter Start_st    = 3'b010;
  parameter SwitchOn_st = 3'b100;
  parameter COUNTER_ON_WIDTH = 23;

  reg [2:0]  st = Start_st;

  always @(posedge clk) begin
    case(st)
      Idle_st : begin
        cnt_i <= 24'h0;
        pulse_out_i <= 1'b0;
        if(pulse_in)
          st <= Start_st;
        else
          st <= Idle_st;
      end

      Start_st : begin
        cnt_i <= 24'h0;
        pulse_out_i <= 1'b1;
        if(pulse_in)
          st <= Start_st;
        else
          st <= SwitchOn_st;
      end

      SwitchOn_st : begin
        cnt_i <= cnt_i + 24'h1;
        pulse_out_i <= 1'b1;
        if(cnt_i[COUNTER_ON_WIDTH]) begin
          st <= Idle_st;
        end
        else begin
          st <= SwitchOn_st;
        end
      end

      default : begin
        cnt_i <= 24'h0;
        pulse_out_i <= 1'b0;
        st <= Idle_st;
      end

    endcase // case (st)
  end

endmodule