20150921
--------

It was found that there is a connection between the testsocket and the
testsocketboard. Visual inspection showed that some bonding wires are
not covered by the glob on the carrier board.

The surface of the plate that press the chip in the testsocket
was isolated with tape on the side to the carrier and a
pressure plate of PC board was also made.

Both were tried but did not solve that problem.

Measuring the resistance between the testsocket and signal traces
on the testsocketboard showed a short between several input signals
and the testsocket.

Two screws on the testsocket was in contact with the signal traces
on the testsocketboard.
These screws were isolated with thin capton tape.
After that no short was measured.

The chip was inserted with the isolated PC board pressure plate 
towards the glob and then the metal plate with tape as isolation.

The chip was tested without any major improvement in performance.

Though it is possible to write and read correct values for some values of
channel and register and data.

The files below are with the result from writing a register
and reading it back.
Values are in hex.
Lines with ERROR have wrong value read back:
ERROR 0 0 RD 00000000 != WR 000003FF
where 
RD XXXXXXX is the value read
WR YYYYYYY is the value written

If correct value is read back then only
VALUE =XXXXXX
is output, where XXXXXX is the written value (in hex).

>Channel 0, register 0 and 8 and A, write a value 0-1023 and read it back.
>PCA and ADC is off

ch0reg0.txt
ch0reg8.txt
ch0regA.txt
ch0regA-1.txt (second try)

>Channel 15, register 0 and 8 and A, write a value 0-1023 and read it back.

ch15reg0.txt
ch15reg8.txt
ch15regA.txt
ch15regA-1.txt (second try)

>Channel 15, register 0 and A, write walking bit and read it back.

ch15reg0-bit.txt
ch15regA-bit.txt

>Channel 15, registe A, write a value 0-1023 and read it back.
>PCA and ADC is on

ch15regA-on.txt
ch15regA-on-1.txt


Try to make a logic out of this!
Some data values are correctly written, some not.
But it is not very reproducible.

When loking on signals do they look as expected when correct,
while when bad there are "signals" after the proper signal.
E.g. ACK has a second short peak with an RC like rise time.

20150923
========


Write a value and then read it back with a working register,
If reading another register in between, and then reading the
correct register again gives wrong value. Have to rewrite it.

>Channel 15, register A, write a walking 0 and read it back.
ch15regA-zero.txt
ch15regA-zero-1.txt
ch15regA-zero-2.txt
ch15regA-zero-3.txt


>Channel 15, register A, write a walking nibble (0x0000F) and read back.
ch15regA-nibble.txt
ch15regA-nibble-1.txt

>Channel 15, register 8 and A, write a walking zero nibble (0xFFFF0) and read back.
ch15regA-nibble0.txt
ch15regA-nibble0-1.txt
ch15reg8-nibble0.txt




20150928
--------

>Channel 15 regA: bits 16-19 incremented, other bits always set.

ch15regA-XFFFF.txt where X= 1->F.

>Channel 15 regA: write DFFFF and read back, repeatedly
>NOTE: DFFFF did never work in walking zero test.

ch15regA-wrDFFFF.txt

>channel 15 walking one with bit 17 always set.
>done since bit 17 gives problems when set to 0 in the DFFFF test.
>here it is forced to be 1 all the time.

ch15regA-bit20000.txt