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Signal timing

The timing of the signals is shown in figure 1. A fixed time (dt1) after a BCO (Beam Cross Over) WNG1 enables the gate generator. During each gate (dt4) the peak sensor is active, and looks for a peak in the incoming sum of the FADs.

If a peak is found and the sum is above the threshold (the or of LOW and HIGH), a peak is indicated. A HOLD to the FADs is sent, followed a fixed time later (dt3) by a HOLD to the strips.

If no peak is found for any of the minibunches in the train, WNG2 disables the gate generator (after the time dt2) and generates the default HOLD signals.

This system is used individually for the four modules, i.e. we may get data from different minibunches for the different modules.

The delay from the time of the peak until the HOLD is sent, may not exceed 100 ns.

The readout is started when the signal READOUT is received from the LTS.

The logic is implemented on a FASTBUS card, described in section 2.2.

Ulf Mjoernmark
Fri Apr 21 14:33:36 METDST 1995