Overview

This section describes in some detail the signal logic, the FASTBUS card and the changes needed on the existing system. It is possible to bypass the logic, in the sense that the HOLD signals are directly taken from WNG1 and WNG2. This will make it possible to run with pre-1995 conditions. This may be useful for debugging and TESTIN runs.

• Signal timing
• FASTBUS card
  • Peak finder and HOLD generation
  • Flash ADC system
  • CPU part
  • Auxilliary backplane
  • CSR space
  • Status registers
  • Serial switch
  • Data readout
  • Data format
• Modifications to 1989-1994 setup
  • FASTBUS auxilliary backplane
  • FASTBUS patch card
  • Cabling
  • Digital patch card
  • Tunnel crate backplane
  • FAD MUX card