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Flash ADC system

The 8-bit flash ADC starts sampling the summed signals at WNG1, and continues until ca 400 ns after the leading edge of WNG2. The time after WNG2 is needed to get the complete shape for the last minibunch. The data is stored in a FIFO (figure 3). The sampling rate is 20 Mhz, i.e. one sample each 50 ns. If the maximum sampling time is 750 ns (Bunchtrain length) + 400 ns = 1150 ns, there is in total 24 32 bit words for each VSAT event.

The number samples to do can be programmed and is is taken from CSR2. The number of samples done is stored in SR3. If any FIFO gets full is a bit set in SR3.

Ulf Mjoernmark
Fri Apr 21 14:33:36 METDST 1995